Manufacture : STMicroelectronics
Category : Integrated Circuits (ICs) - Embedded Microcontrollers
Core Processor : ARM® Cortex®-M3
Core Size : 32-Bit Single-Core
Speed : 72MHz
Connectivity : CANbus, I2C, IrDA, LINbus, SPI, UART/USART, USB
Peripherals : DMA, Motor Control PWM, PDR, POR, PVD, PWM, Temp Sensor, WDT
Number of I/O : 51
Program Memory Size : 512KB (512K x 8)
RAM Size : 64K x 8
Voltage - Supply (Vcc/Vdd) : 2V ~ 3.6V
Data Converters : A/D 16x12b; D/A 2x12b
STM32F103RET6 the performance line family incorporates the high-performance Arm® Cortex®-M3 32-bit RISC core operating at a 72 MHz frequency, high-speed embedded memories (Flash memory up to 512 Kbytes and SRAM up to 64 Kbytes), and an extensive range of enhanced I/Os and peripherals connected to two APB buses. All devices offer three 12-bit ADCs, four general-purpose 16-bit timers plus two PWM timers, as well as standard and advanced communication interfaces: up to two I2Cs, three SPIs, two I2Ss, one SDIO, five USARTs, an USB and a CAN.
The stm32f103ret6 high-density performance line family operates in the –40 to +105 °C temperature range, from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving mode allows the design of low-power applications.
These features make the stm32f103ret6 high-density performance line microcontroller family suitable for a wide range of applications such as motor drives, application control, medical and handheld equipment, PC and gaming peripherals, GPS platforms, industrial applications, PLCs, inverters, printers, scanners, alarm systems video intercom, and HVAC.
Arm® Cortex®-M3 core with embedded Flash and SRAM
The Arm Cortex®-M3 processor is the latest generation of Arm processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts.
The Arm Cortex®-M3 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an Arm core in the memory size usually associated with 8- and 16-bit devices.
With its embedded Arm core, STM32F103xC, STM32F103xD and STM32F103xE
performance line family is compatible with all Arm tools and software.
FSMC (flexible static memory controller)
The FSMC is embedded in the stm32f103ret6 performance line family. It has four Chip Select outputs supporting the following modes: PC Card/Compact Flash, SRAM, PSRAM, NOR and NAND. Functionality overview:
• The three FSMC interrupt lines are ORed in order to be connected to the NVIC
• Write FIFO
• Code execution from external memory except for NAND Flash and PC Card
• The targeted frequency, fCLK, is HCLK/2, so external access is at 36 MHz when HCLK is at 72 MHz and external access is at 24 MHz when HCLK is at 48 MH
Nested vectored interrupt controller (NVIC)
The stm32f103ret6 performance line embeds a nested vectored interrupt controller able to handle up to 60 maskable interrupt channels (not including the 16 interrupt lines of Cortex®-M3) and 16 priority levels.
• Closely coupled NVIC gives low latency interrupt processing
• Interrupt entry vector table address passed directly to the core
• Closely coupled NVIC core interface
• Allows early processing of interrupts
• Processing of late arriving higher priority interrupts
• Support for tail-chaining
• Processor state automatically saved
• Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimal interrupt latency
Low-power modes
The stm32f103ret6 performance line supports three low-power modes to achieve the best compromise between low-power consumption, short startup time and available wakeup sources:
• Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs.
• Stop mode
Stop mode achieves the lowest power consumption while retaining the content of SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low-power mode.
The device can be woken up from Stop mode by any of the EXTI line. The EXTI line source can be one of the 16 external lines, the PVD output, the RTC alarm or the USB wakeup.
• Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.8 V domain is powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering Standby mode, SRAM and register contents are lost except for registers in the Backup domain and Standby circuitry.
The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a rising edge on the WKUP pin, or an RTC alarm occurs.
Timers and watchdogs
The high-density stm32f103ret6 performance line devices include up to two advanced control timers, four general-purpose timers, two basic timers, two watchdog timers, and a SysTick timer.
General-purpose timers (TIMx)
There are up to 4 synchronizable general-purpose timers (TIM2, TIM3, TIM4, and TIM5) embedded in the stm32f103ret6 performance line devices. These timers are based on a 16-bit auto-reload up/down counter, and a 16-bit prescaler and feature 4 independent channels each for input capture/output compare, PWM, or onepulse mode output. This gives up to 16 input captures/output compares / PWMs on the largest packages.
The general-purpose timers can work with the advanced-control timer via the Timer Link feature for synchronization or event chaining. Their counter can be frozen in debug mode. Any of the general-purpose timers can be used to generate PWM outputs. They all have independent DMA request generation.
These timers can handle quadrature (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors.
The stm32f103ret6 performance line embeds three universal
synchronous/asynchronous receiver transmitters (USART1, USART2, and USART3) and two universal asynchronous receiver transmitters (UART4 and UART5).
These five interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire half-duplex communication mode, and LIN Master/Slave capability.
The USART1 interface can communicate at speeds of up to 4.5 Mbit/s. The other available interfaces communicate at up to 2.25 Mbit/s.
USART1, USART2, and USART3 also provide hardware management of the CTS and RTS signals, Smart Card mode (ISO 7816 compliant), and SPI-like communication capability. All interfaces can be served by the DMA controller except for UART5.
Universal serial bus (USB)
The STM32F103xE performance line embed a USB device peripheral compatible with the USB full-speed 12 Mbs. The USB interface implements a full-speed (12 Mbit/s) function interface. It has software-configurable endpoint setting and suspend/resume support. The dedicated 48 MHz clock is generated from the internal main PLL (the clock source must use a HSE crystal oscillator).
ADC (analog to digital converter)
Three 12-bit analog-to-digital converters are embedded into STM32F103xE performance line devices and each ADC shares up to 21 external channels, performing conversions in single-shot or scan modes. In scan mode, automatic conversion is performed on a selected group of analog inputs.
Additional logic functions embedded in the ADC interface allow:
• Simultaneous sample and hold
• Interleaved sample and hold
• Single shunt
The ADC can be served by the DMA controller.
An analog watchdog feature allows very precise monitoring of the converted voltage of one,some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds.
The events generated by the general-purpose timers (TIMx) and the advanced-control timers (TIM1 and TIM8) can be internally connected to the ADC start trigger and injection trigger, respectively, to allow the application to synchronize A/D conversion and timers.
DAC (digital-to-analog converter)
The two 12-bit buffered DAC channels can be used to convert two digital signals into two analog voltage signal outputs. The chosen design structure is composed of integrated resistor strings and an amplifier in an inverting configuration.
This dual digital Interface supports the following features:
• two DAC converters: one for each output channel
• 8-bit or 12-bit monotonic output
• left or right data alignment in 12-bit mode
• synchronized update capability
• noise-wave generation
• triangular-wave generation
• Dual DAC channel independent or simultaneous conversions
• DMA capability for each channel
• external triggers for conversion
• input voltage reference VREF+
Eight DAC trigger inputs are used in the STM32F103xE performance line family. The DAC channels are triggered through the timer update outputs that are also connected to different DMA channels.
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